A pel-based Volume Rendering Accelerator

We discuss the underlying algorithms, design principles and implementation issues of an extremely compact and cost-efficient volume rendering accelerator for PCI-based systems. It operates on classified and shaded data sets which have been coded and compressed using Redundant Block Compression (RBC), a tech­ nique originating from 2D-imaging and extended to 3D. This specific encoding scheme reduces drastically the required data traffic between the volume memory and the processing units. Thus, the volume data set can be placed into the main memory of the host, eliminating the need of a separate volume memory. Fur­ thermore, the tri-Iinear interpolation needed for perspective raycasting is very much simpli­ fied for RBC-transformed data sets. All in all, these techniques allow a volume ren­ dering accelerator to be implemented as a sin­ gle-chip coprocessor, or as an FPGA-based prototype for monochrome data sets as pre­ sented in this work. Although using a lossy compression scheme, image quality is still high, and expected frame rates are between 2 and 5Hz for typical data sets of 2563 voxels.